1. Field of the Invention
The present invention concerns a circuit for the detection of address transitions in an integrated circuit. To reduce consumption by integrated circuits, it is becoming increasingly common to activate them only when there is a change, at the input terminal, in the level of the address signals or validation signals of the circuit. When nothing happens, the consumption of the circuit is low but all the same, it is not zero. Circuits to detect transitions of addresses are already known and enable the detection of a change in level or of the leading edge at the input terminal.
2. Description of the Prior Art
Commonly used circuits are generally made up of chains of inverters. The detection method consists in measuring the level of the signals at different points of this chain and in combining them in logic gates with the input signal so as to obtain an output pulse as soon as there is a change in level at the input terminal.
Unfortunately, the pulse generated at the output terminal as soon as there has been a change in level at the input terminal is necessarily delayed by the propagation time in the inverters, for the circuit is series-connected. Furthermore, the duration of the pulse and its time delay with respect to the transition are related and are a function of the transfer time in the inverters. If a wide pulse is sought so that it can be used properly, its time delay will be all the greater.
To overcome these drawbacks, the invention proposes a circuit for the detection of address transitions which minimizes the time delay in the pulse generated at the output terminal as soon as there is a change in level at the input terminal.